1. Field of the Invention
The invention relates to a clock generator, and more particularly to a device and the method thereof for respectively tuning frequencies of a plurality of clock signals generated by a clock generator.
2. Description of the Related Art
In general, a conventional PC (Personal Computer) has a clock chip for providing various clock signals for elements disposed on a motherboard, such as a CPU (Central Processor Unit), peripheral chips, and buses. Because the tolerance of the working frequency of these chips and buses have been taken into account in the design stage, overclocking operations may be executed by the clock chip on these elements, so as to increase the working frequencies of the elements and thus the system's efficiency are enhanced.
FIG. 1 is an architecture diagram showing chips disposed on a motherboard. These chips comprise a CPU 110, a north bridge chip 120, a south bridge chip 130 and a clock chip 140. When the overclocking operation is to be executed by the clock chip, a watchdog timer 141 inside the clock chip 140 is first set. Next, the watchdog timer 141 is enabled, and then the following overclocking operation is executed. The clock chip 140 increases the frequency of a clock signal and then outputs the clock signal to the element corresponding to the clock signal. Consequently, the system of the motherboard will be checked to determine whether the system of the motherboard works normally or not after increasing the frequency of the clock signal.
For example, the clock chip 140 increases the frequency of the clock signal (CPU_CLK) provided for the CPU 110 from 100 MHz to 101 MHz, and then the CPU 110 is operated according to the CPU_CLK. Meanwhile, the CPU 110 executes a BIOS (Basic Input/Output System) program and thus the south bridge chip 130 generates the SCLK and SDATA signals to reset the watchdog timer 141. If the CPU is workable according to the frequency (101 MHz) of CPU_CLK, the watchdog timer 141 can be reset before it generates an interrupt signal. Furthermore, the clock chip 140 sets the frequency (101 MHz) as a safe frequency Fsafe of the CPU_CLK, and increases the frequency of the CPU_CLK from 101 MHz to 102 MHz.
If the CPU 110 is unworkable according to the frequency (102 MHz) of the CPU_CLK, the CPU 110 cannot execute the BIOS program and thus the south bridge chip 130 cannot output the SCLK and SDATA signals to reset the watchdog timer 141. Thus, the watchdog timer 141 generates an interrupt signal and the clock chip 140 sets the frequency of the CPU_CLK equal to Fsafe (101 MHz). Then the system of the motherboard is reset.
However, the conventional clock chip 140 outputs various clock signals which correlate to one another. That is, if the overclocking operation executed on the clock signal provided for the accelerated graphics port (AGP) 121 fails, other clock signals (e.g., CPU_CLK) cannot continuously be overclocked. Hence, the overclocking range of each of the chips, buses or other elements, which operates according to the clock signal outputted from the clock chip 140, is restricted by the element having the smallest overclocking tolerance. Moreover, the timing period of resetting the watchdog timer 141 is too long so that the clock chip 140 has to spend a lot of time to perform the overclocking operation. Therefore, the overclocking method of the conventional clock chip still has some drawbacks to be overcome.